Main Design Requirements
- Easy to build on a breadboard
- Simple serial terminal access
- GPIO for interfacing to the outside world
- Enough RAM & ROM to do something interesting
Hardware Design
Major Components
Amazingly, WDC is still producing the 6502 and it’s support chips. I was able to purchase these from Mouser.
| Device | Part No | Description | Datasheet |
|---|---|---|---|
| 65c02 CPU | W65C02S6TPG-14 | WDC 6502 processor capable of 14MHz! | Link |
| 6522 VIA | W65C22S6TPG-14 | WDC 6522 Versatile Interface Adapter | Link |
| 6551 ACIA | W65C51N6TPG-14 | WDC 6551 Asynch Communication Interface Adapter | Link |
| 62256 | AS6C62256-55PCN | 32k x 8 SRAM | Link |
| 28C256 | AT28C256-15PU | 32k x 8 EEPROM | Link |
| 74HC00 | CD74HC00EE4 | Quad 2-input NAND Gate | Link |
| DS1813 | DS1813-5+T&R | Econoreset | Link |
Schematic
Due to the way I built this machine up over time, I don’t actualy have a full schematic for it. In all honesty, there’s not that much to it. A0:A15, D0:D7 go to their matching signals on each device, power bypass filter caps (CMOS logic) go next to every chip, and we are left with two interested parts of the build.
The first is the econoreset supervisory circuit - using the DS1813 resulted in a very simple reset circuit that cold-starts & resets reliably. There are LOTS of reset circuits out there, and this one is probably the simplest, most reliable, uses the least components, etc…
The second is the address decoding logic. Here I used an interesting design from Garth Wilson’s 6502 Primer to do all the address decoding with a single quad NAND gate. This gives us 32k ROM, 16k RAM, and a few IO devices in the no man’s land between them.
Memory Map
| Begin | End | Description |
|---|---|---|
| 0000 | 00FF | Zero Page |
| 0100 | 01FF | Stack |
| 0300 | 3FFF | 16k RAM |
| 4400 | 4403 | ACIA |
| 6000 | 600F | VIA |
| 8000 | FFFF | 32k ROM |
| FFFA | FFFF | Reset/Interrupt Vectors |
Some notes regarding the memory map above:
- “Zero Page” on the 6502 is used as a full page of 8 bit registers.
- The second page (01) is used for the hardware stack.
- Zero page & the stack are stored in RAM, but called out here as they serve special purposes in the 6502 architecture.
- Due to the simple memory map decoding, the I/O devices actually appear in multiple places, but only the intended location is documented. Reading from non-decoded memory locations will read whatever happens to be on the data bus at the time.
- Reset/Interrupt vectors is a jump table, with pointers to the reset, interrupt, and non-maskable interrupt vectors.